14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

Author

Zuow-Zun Chen ; Yen-Hsiang Wang ; Jaewook Shin ; Yan Zhao ; Mirhaj, Seyed Arash ; Yen-Cheng Kuan ; Huan-Neng Chen ; Chewn-Pu Jou ; Ming-Hsien Tsai ; Fu-Lung Hsueh ; Chang, Mau-Chung Frank

Author_Institution

Univ. of California, Los Angeles, Los Angeles, CA, USA

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL´s high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

Keywords

frequency synthesizers; phase detectors; phase locked loops; time-digital conversion; all-digital phase-locked loop; analog voltage signal; divider feedback; in-band phase noise; reference signal; subsampling all-digital fractional-N frequency synthesizer; subsampling phase detection; time-to-digital conversion technique; time-to-digital converter; Calibration; Frequency synthesizers; Jitter; Phase locked loops; Phase noise; Power demand; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7063029

Filename

7063029