Title :
A Tool for Exploring Hybrid FPGAs
Author_Institution :
Imperial Coll. London, London
Abstract :
We show that the VPH tool can accurately model a commercial FPGA on a set of benchmark problems. It is able to model heterogeneous embedded blocks in a hybrid FPGA and facilitates design exploration. This tool combines the benefits of both the VPR and the VEB. VPR allows a larger FPGA architecture design space to be evaluated than commercial tools, and VEB enables analysis of hybrid FPGAs. Current and future work includes extending VPH to cover other devices, using VPH to explore the performance of hybrid FPGAs in various architectures, and developing automated algorithms to optimize the hybrid FPGAs for domain specific applications.
Keywords :
field programmable gate arrays; logic design; optimisation; heterogeneous embedded block; hybrid FPGA architecture design; optimization; Delay; Energy consumption; Fabrics; Field programmable gate arrays; Logic devices; Performance analysis; Programmable logic arrays; Routing; Switches; Timing;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380703
