A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

This paper presents an approach for efficiently mapping loops and array intensive applications onto FPGA architectures with distributed RAMs, multipliers and logic. We perform a data dependency based, two level partitioning of the application´s iteration space under target FPGA architectural constraints, to achieve better performance. It is shown that, this approach can result in a super-linear speedup; linear speedup due to concurrent computation on multiple compute elements and additional speedup due to improvement in the clock frequency (up to 30%). The clock period reduction is made possible because computation and accesses are now localized, i.e. the compute elements interact only with memories which are close by.