Title :
Test considerations for BiCMOS logic families
Author :
Roy, Kaushik ; Levitt, Marc E. ; Abraham, Jacob A.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
The testability of various BiCMOS logic families is examined. For each design style the adequacy of stuck-at and quiescent current testing is explored. It is shown that while stuck-at and Iddq testing can cover many faults there are still a large number of faults that are not detectable. Using the results presented the various logic families can be ranked by testability when being evaluated for an application
Keywords :
BIMOS integrated circuits; application specific integrated circuits; integrated circuit testing; logic testing; BiCMOS; delay faults; logic families; quiescent current testing; stuck-at faults; stuck-at testing; test considerations; testability; Application specific integrated circuits; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Fault detection; Inverters; Logic testing; MOS devices;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164011
