DocumentCode :
2063909
Title :
Mapping a VLIWÃ\x97SIMD Processor on an FPGA: Scalability and Performance
Author :
Nelissen, Micha ; Van Berkel, Kees ; Sawitzki, Sergei
Author_Institution :
Eindhoven Univ. of Technol., Eindhoven
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
521
Lastpage :
524
Abstract :
This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2middot109 vector operations per second. For classical real-world DSP benchmarks around 1...3middot108 vector operations per second can be achieved.
Keywords :
digital signal processing chips; field programmable gate arrays; instruction sets; parallel architectures; parallel machines; vector processor systems; FPGA devices; VLIW instruction per clock cycle; VPF VLIW SIMD processor architecture; Xilinx Virtex-4 device; digital signal processing; field programmable gate arrays; vector processing; very long instruction word machines; Application software; Clocks; Computer architecture; Decoding; Digital signal processing; Field programmable gate arrays; Modems; Registers; Scalability; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
Type :
conf
DOI :
10.1109/FPL.2007.4380707
Filename :
4380707
Link To Document :
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