Title :
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS
Author :
Kramer, Martin ; Janssen, Erwin ; Doris, Kostas ; Murmann, Boris
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
In this paper the authors present a 14b 35MS/s SAR ADC in 40nm CMOS with a loop-embedded input buffer that consumes 23% of the total ADC power. The buffer uses a source follower (SF) topology whose nonlinearities are cancelled by the SAR algorithm, enabling 99dB SFDR despite the small amount of invested power.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; CMOS; SAR ADC; SF topology; analog-to-digital converters; loop-embedded input buffer; size 40 nm; source follower topology; successive-approximation-register; CMOS integrated circuits; Capacitance; Capacitors; Clocks; Switches; Timing; Topology;
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
DOI :
10.1109/ISSCC.2015.7063037
