Title :
A 40MHZ dedicated hardware H.264/AVC video encoder with the reducing memory access scheme
Author :
Lee, Sukho ; Park, SeongMo ; Han, Jinho ; Eum, Nakwoong ; Park, Jongwon
Author_Institution :
SoC Res. Dept., Electron. & Commun. Telecommun. Res. Inst., Daejeon
Abstract :
In this paper, we present the dedicated hardware H.264/AVC video encoder with reducing memory access scheme. This engine performs 30 frame/sec with D1(720x480) resolution at 40 MHz. It has dedicated hardware architecture, memory reducing scheme, double buffering structure to decrease memory bus bandwidth and early decision mode for fast estimation at motion estimation. It supports to H.264/AVC base profile level 3. Its gate count is 427K and can be applied various application, such as, IPTV, surveillance system and portable multimedia devices to need low frequency and low power.
Keywords :
image resolution; motion estimation; video coding; H.264/AVC video encoder; IPTV; dedicated hardware; double buffering structure; frequency 40 MHz; memory access scheme; memory bus bandwidth; motion estimation; portable multimedia devices; surveillance system; Automatic voltage control; Bandwidth; Engines; Frequency; Hardware; IPTV; Memory architecture; Motion estimation; Multimedia systems; Surveillance; 40MHz; H.264; encoder; reducing memory access scheme;
Conference_Titel :
Consumer Electronics, 2008. ISCE 2008. IEEE International Symposium on
Conference_Location :
Vilamoura
Print_ISBN :
978-1-4244-2422-1
Electronic_ISBN :
978-1-4244-2422-1
DOI :
10.1109/ISCE.2008.4559542
