A high performance VLSI architecture for integer motion estimation in HEVC

Author

Xu Yuan ; Liu Jinsong ; Gong Liwei ; Zhang Zhi ; Teng, Robert K. F.

Author_Institution

Shenzhen Key Lab. of Adv. Commun. & Inf. Process., Shenzhen Univ., Shenzhen, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

A high performance VLSI architecture for integer motion estimation (IME) in High Efficiency Video Coding (HEVC) is presented in this paper. It supports coding tree block (CTB) structure with the asymmetric motion partition (AMP) mode. The architecture contains two parallel sub-architectures to meet 1080p@30fps real-time video coding. The size L×L of CTB in the architecture is set to L=32 pixels by default, and it can be extended to L=64 and L=16 pixels. A serial mode decision module to find optimal partition mode for the architecture has also been implemented.

Keywords

VLSI; motion estimation; performance evaluation; video coding; AMP mode; CTB; HEVC; IME; asymmetric motion partition; coding tree block; high efficiency video coding; high performance VLSI architecture; integer motion estimation; optimal partition mode; parallel subarchitectures; Arrays; Clocks; Encoding; Motion estimation; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811845

Filename

6811845