A Novel Motion Estimation Power Reduction Technique

A method is proposed to reduce the power used in the motion estimation stage of an FPGA based H.264 video encoder. Distinguishing it from other algorithms is its use of information generated during the rest of the encoding process, specifically, the intra prediction stage. Using the results of the intra prediction stage, a simple algorithm determines the direction with which to propagate reference data through the systolic array, used for motion estimation, in order to minimize the array´s switching activity. Results are given showing that this method can reduce the switching activity, and hence power, in the array by up-to 10%. The reduction achievable is, however, conditional on reducing the bit-width of the inputs to the motion estimation process.