An optimized hardware architecture for intra prediction in H.264 decoder

The advanced video coding standard H.264 is widely used to compress video data for applications such as Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance Video. Intra prediction is one of the most critical issues in H.264 decoding in terms of processing cycles and computation complexity, it is the system bottleneck of real-time H.264 decoding. This paper presents an area optimized memory update mechanism. For luma 4×4 block prediction, the proposed architecture only adds four registers to store the corner pixels based on luma 16×16 block prediction. A high efficient 4×4 block level pipeline is also presented in this paper. The pipelined architecture eliminates data dependencies between two neighboring blocks thoroughly by inserting chroma 4×4 block processing into luma 4×4 block processing. The proposed architecture is verified to work at 160MHz in a Xilinx Virtex-II pro FPGA. It costs about 23k gates by using SIMC 90nm technology and supports real-time decoding with 1080p format video in 30fps.