A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder

The adoption of 35 prediction modes and quad-tree structure in intra coding of High Efficiency Video Coding (HEVC) significantly improves the coding efficiency. In this paper, a highly pipelined 16-pixel parallel VLSI architecture of intra prediction in HEVC encoder is proposed, supporting all prediction modes and all block sizes. Original pixels are used to help to decide prediction mode and block partition in the premise of negligible PSNR degradation, and a universal predictor is presented. In order to reduce internal buffers when scanning full-mode and full-size predictions in encoder, post-order traversal is applied to the quad-tree structure blocks. It takes 8967 cycles to complete the intra prediction of a whole 32×32 treeblock, including prediction and the decision of mode and block partition. This design is synthesized with TSMC 65nm CMOS technology. It can run at 600 MHz, supporting real-time encoding of 1080P@30fps video sequence.