Title :
A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA
Author :
Claver, J.M. ; Agustí, P. ; León, G. ; Canseco, M.
Author_Institution :
Valencia Univ., Valencia
Abstract :
Nowadays, high performance system/local area networks (SAN/LAN) are filled by heterogeneous traffic, consisting of information flows with different bandwidth and latency requirements. The bottleneck produced by the throughput of network processing elements (servers, routers,...) and the increasing bandwidth of links, makes it necessary to propose new designs for these network components. The MMR (and its simplified version, the SMMR), a router that supports QoS, is a very well-known proposal in this area. In this article we propose the architecture and implementation of a hardware reprogrammable traffic multimedia generator/monitor (G/M) to study these sorts of routers under different traffic conditions and server models.
Keywords :
field programmable gate arrays; local area networks; multimedia communication; quality of service; telecommunication network routing; telecommunication traffic; FPGA; bandwidth requirements; hardware reprogramming; information flows; latency requirements; local area networks; multimedia traffic generator; multimedia traffic monitor; quality of service; router; server models; system area networks; Bandwidth; Delay; Field programmable gate arrays; Local area networks; Monitoring; Network servers; Storage area networks; Telecommunication traffic; Throughput; Traffic control;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380718
