A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA

Nowadays, high performance system/local area networks (SAN/LAN) are filled by heterogeneous traffic, consisting of information flows with different bandwidth and latency requirements. The bottleneck produced by the throughput of network processing elements (servers, routers,...) and the increasing bandwidth of links, makes it necessary to propose new designs for these network components. The MMR (and its simplified version, the SMMR), a router that supports QoS, is a very well-known proposal in this area. In this article we propose the architecture and implementation of a hardware reprogrammable traffic multimedia generator/monitor (G/M) to study these sorts of routers under different traffic conditions and server models.