A high-resolution TDC implemented in a 90nm process FPGA

This paper represents a Time-to-digital Converter (TDC) architecture based in a FPGA. The proposed architecture relies on a single tapped-delay line to implement time-to-digital conversion, taking advantage of the fast dedicated carry chains available within FPGAs. The results of post-route simulation indicate that this architecture offered a time resolution of 34ps with a 12 ps precision. In a Virtex-4 FPGA that is fabricated in the 90nm process this structure achieved a resolution of 48ps and a precision of 35ps.Commonly, to design a TDC on a FPGA requires iterative manual adjustment in the placement and route of the circuit; however, in the architecture presented in this paper, we controls the performance of pivotal parts of the circuit with user constraints instead of manual adjustment, which makes this TDC architecture access to portability.