Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

Author

Lightbody, Gaye ; Woods, Roger ; Francey, Jonathan

Author_Institution

Ulster Univ., Jordanstown

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

597

Lastpage

600

Abstract

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilias Virtex 4 FPGA giving a 5 GFLOPS performance.

Keywords

field programmable gate arrays; hardware description languages; least squares approximations; recursive filters; QR-based recursive least squares filter design; Xilias Virtex 4 FPGA; additive operators; circuit architecture; multiplicative operators; parameterisable HDL descriptions; soft IP core implementation; Arithmetic; Circuits; Computer architecture; Field programmable gate arrays; Filtering; Filters; Least squares methods; Pipeline processing; Resonance light scattering; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Conference_Location

Amsterdam

Print_ISBN

978-1-4244-1060-6

Electronic_ISBN

978-1-4244-1060-6

Type

conf

DOI

10.1109/FPL.2007.4380725

Filename

4380725