Title :
Performance trade-offs and optimization of low side low voltage integrated FETs
Author :
Pendharkar, Sameer ; Ramanathan, Rarnani ; Efland, Taylor ; Zheng, Liqing
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.
Keywords :
doping profiles; isolation technology; optimisation; power MOSFET; MOS power device; doping profile optimization; integrated FET performance trade-offs; isolated drain LDMOS; lateral FET; lateral diffused MOS structure; low side low voltage FET; p-substrate junction isolation technologies; thin resurf LDMOS devices; Bridge circuits; Diodes; Doping; FETs; Inductors; Isolation technology; Low voltage; Positron emission tomography; Pulse width modulation; Roentgenium;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting
Print_ISBN :
0-7803-8618-3
DOI :
10.1109/BIPOL.2004.1365769
