High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs

We describe the optimization of power consumption obtained by a high level environment developed for the automatic generation of application specific circuits on FPGA. The methodology used is based on the transformation of the whole algorithm in a graph of LUTs that implements all the required operations without the use of library components. The quality of the obtained circuitry is guaranteed by the use of "type inference". Our environment automatically optimizes the word-length and size of operators, and at the same time, reduces the internal data paths and the switching activity. Thus, in the extreme cases tested, the resulting generated circuits offer an important improvement in area usage of up to 95%, and power consumption is reduced by up to 98%.