Title :
RIC Fast Adder and its Set-Tolerant Implementation in FPGAs
Author :
Mesquita, Eduardo ; Franck, Helen ; Agostini, Luciano ; Guntzel, Jose Luis
Author_Institution :
Fed. Univ. of Pelotas, Pelotas
Abstract :
FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are fabricated with nanometer CMOS technology that is becoming susceptible to radiation-induced soft errors. Among these errors, single-event transients (SETs) are those that are induced in the user´s programmable logic. This paper presents a new fast adder, called RIC (Re-computing the Inverse Carry-in) and shows how this new adder architecture may be used to build SET-tolerant fast adders. Results considering FPGA-based implementation are presented.
Keywords :
CMOS logic circuits; adders; carry logic; field programmable gate arrays; FPGA device; RIC adder; SET-tolerant implementation; field programmable gate array; nanometer CMOS technology; recomputing-inverse carry-in; single-event transients; Adders; CMOS logic circuits; CMOS technology; Costs; Field programmable gate arrays; Logic design; Logic devices; Nanoscale devices; Programmable logic arrays; Time to market;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380735
