Folding and interpolation ADC design methodology

High-speed low-power ADCs with medium resolution (8 to 10 bits) are important building blocks for high performance systems, such as wide band communication data links and electrical testers. Folding and interpolation ADC balances power consumption with accuracy, which makes it a good candidate for such applications. With reduced power supply voltage in advanced IC processes, device random offset induced error becomes the main limit to performance of folding and interpolation ADCs. A key design challenge is to improve linearity by suppressing the device random offset without significantly increasing area and power. This paper presents operation principle of folding and interpolation ADCs and a design method for reducing random offset introduced errors, which is validated by an ADC of 57dB SNDR at 500Msps designed in a 0.18μ BiCMOS.