• DocumentCode
    2064739
  • Title

    Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

  • Author

    Siozios, K. ; Sotiriadis, K. ; Pavlidis, V.F. ; Soudris, D.

  • Author_Institution
    Democritus Univ. of Thrace, Thrace
  • fYear
    2007
  • fDate
    27-29 Aug. 2007
  • Firstpage
    652
  • Lastpage
    655
  • Abstract
    This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPR0 for placement and routing on 3D FPGAs and (ii) the 3DPower for power/energy estimation on such architectures. We mainly focus our exploration on the total number of layers and the amount of vertical interconnects (or vias). The efficiency of the proposed architecture is evaluated by making an exhaustive exploration for via connections under the Energy x Delay Product criterion. Experimental results demonstrate the effectiveness of our solution, considering the 20 largest MCNC benchmarks. Considering 3D architectures with 4 layers and two scenarios of fabricated via densities (30% and 70%), we achieve an average decrease in the delay, the wire length, and the energy consumption of 18%, 17%, and 31%, respectively, as compared to 2D FPGAs. We also achieved high utilization of vias links.
  • Keywords
    field programmable gate arrays; logic CAD; 3D FPGA architecture; energy consumption; energy estimation; logic CAD; power estimation; Delay; Design automation; Design methodology; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Manufacturing industries; Routing; Switches; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
  • Conference_Location
    Amsterdam
  • Print_ISBN
    978-1-4244-1060-6
  • Electronic_ISBN
    978-1-4244-1060-6
  • Type

    conf

  • DOI
    10.1109/FPL.2007.4380738
  • Filename
    4380738