• DocumentCode
    2064767
  • Title

    An FPGA Based Memory Efficient Shared Buffer Implementation

  • Author

    Burns, Dwayne ; Toal, Ciaran ; McLaughlin, Kieran ; Sezer, Sakir ; Hutton, Mike ; Cackovic, Kevin

  • Author_Institution
    Queen´´s Univ. Belfast, Belfast
  • fYear
    2007
  • fDate
    27-29 Aug. 2007
  • Firstpage
    661
  • Lastpage
    664
  • Abstract
    This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.
  • Keywords
    DRAM chips; field programmable gate arrays; FPGA based memory efficient shared buffer implementation; RLDRAM II; high capacity shared buffer designs; high-speed hardware architectures; Delay; Field programmable gate arrays; Hardware; IP networks; Memory architecture; Quality of service; Random access memory; Scheduling algorithm; Telecommunication traffic; Time division multiplexing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
  • Conference_Location
    Amsterdam
  • Print_ISBN
    978-1-4244-1060-6
  • Electronic_ISBN
    978-1-4244-1060-6
  • Type

    conf

  • DOI
    10.1109/FPL.2007.4380740
  • Filename
    4380740
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2064767