A reference spur estimation method for integer-N PLLs

The reference spur level is one of the big challenges during the PLL design. Caused by many reasons such as the timing/current mismatch and the leakage current from the PFD/CP and loop filter (LF), the reference spur is hard to be predicted. Using the novel open-loop algorithm instead of the traditional close-loop method, the proposed method allows for the quick prediction of the spur level during the design of the PLL building blocks, i.e., before the end of full PLL. In this paper, the spur transfer function is derived, and the method is implemented in Verilog-A. The prediction results match well with the close-loop transistor-level simulation.