Title :
Improved techniques for high performance noise-tolerant domino CMOS logic circuits
Author :
Sarma, D.S.V.S. ; Mahapatra, Kamala Kanta
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India
Abstract :
Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is designed. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realize wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness.
Keywords :
CMOS logic circuits; leakage currents; logic design; logic gates; continuous scaling; dynamic CMOS gates design; evaluation network; fan-in gates; high noise sensitivity; high performance noise-tolerant domino CMOS logic circuits; high-performance design; noise robustness; size 90 nm; subthreshold leakage current; Leakage current; Logic gates; MOSFETs; Manganese; Noise; Partial discharges; Domino logic; leakage current; noise tolerance; power consumption;
Conference_Titel :
Engineering and Systems (SCES), 2012 Students Conference on
Conference_Location :
Allahabad, Uttar Pradesh
Print_ISBN :
978-1-4673-0456-6
DOI :
10.1109/SCES.2012.6199119
