Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors

This paper describes a number of microarchitectural techniques for supporting multithreading in soft processor cores. These include a new thread scheduler that combines interleaved and block multithreading; a table of operation latencies (TOOL) for determining instruction latencies; support of arbitrary-latency custom computational units; and a multi-banked register file for supporting simultaneous write-back operations from different threads. Our results show that four-way, multithreaded, processors achieve speedups of up to 26% over a single-threaded processor executing benchmarks that only use regular instructions, and up to 47% when executing benchmarks that include long-latency instructions.