A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation

An algorithm and architecture for a hardware based simulation accelerator is presented. The accelerator can perform full timing simulation of synchronous digital circuits described at the gate level. The simulator makes use of a cycle based processor core in conjunction with event queues to execute the simulation. By ensuring that the gates are evaluated in rank order, the problem of sorting event queues is avoided. Static scheduling of the gates at compile time allows a simple control structure for the run time. The simple architecture allows large processing arrays to be implemented on relatively simple hardware. Results on ISCAS89 benchmark circuits are presented to demonstrate the scalability with hardware resources.