Robust current-mode on-chip interconnect signaling scheme in deep submicron

In this paper, we propose a novel process-variation robust current-mode signaling scheme for on-chip interconnects. By using special bias generation circuits in the driver, the current-mode signaling system is robust in the presence of process induced parameter variations and uncertainties. Different process corners and Monte Carlo simulation analyses are carried out using Hspice in Chartered Semiconductor 0.18 micrometer process. The process corner simulation analyses show that the average power and system delay don´t change much in different process corner, especially in typical, FS and SF corner. Monte Carlo analyses show that the average delay and power of the interconnect signaling system are normally distributed for a 10mm wire in 180 nm process technology.