A tool towards integration of IC process, device, and circuit simulation

Author

Chin, Goodwin ; Yu, Zhiping ; Dutton, Robert W.

Author_Institution

Integrated Circuits Lab., Stanford Univ., CA, USA

fYear

1991

fDate

12-15 May 1991

Abstract

An interactive tool suitable for accurate characterization of arbitrary submicron devices is presented. The tool uses a transparent link with device simulation to obtain more accuracy than is possible with analytic models. While the tool can be used to generate typical device characteristics (I-V curves and delay analysis) useful for sensitivity analysis and analytic model development, a greater benefit of the tool is its ability to analyze parasitic devices that may lead to reliability problems. These parasitic devices are extremely difficult to characterize and tend to be overlooked. The tool is used to investigate the influence of these parasitics by analyzing the effect of layout on the latchup characteristics of a standard cell

Keywords

circuit analysis computing; integrated circuit technology; interactive systems; sensitivity analysis; I-V curves; IC process; analytic model development; circuit simulation; delay analysis; device simulation; interactive tool; latchup characteristics; layout; parasitic devices; sensitivity analysis; standard cell; submicron devices; Analytical models; Character generation; Circuit simulation; Computational modeling; Data mining; Delay; Doping profiles; Laboratories; MOSFETs; Mesh generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164017

Filename

164017