Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs

Dynamic Partially Reconfiguration (DPR) designs based on FPGA is an attractive and challenging technique which could reuse the same hardware for different tasks at different phases during the execution of an application. Though DPR can improve the resource utilization with reduced power consumption, the critical bottleneck is the overhead caused by the online-reconfiguration. To overcome the performance degradation of DPR, configuration prefetching technique could be used by parallelizing the reconfiguration periods with the execution of other tasks. However, the prefetching scheme should be constrained by the data dependency relations between tasks, which makes the design of the prefetching schedule quite complicated. Thus, in this paper, we formulate the optimization of prefetch scheduling with module-based data dependency graph so that the reconfiguration overhead could be minimized efficiently. Our experiments show that our algorithm performs significantly better than the state-of-art prefetching algorithms with 19.2% reduction of the execution time of PR regions. Compared with the enumeration method which should provide the optimal solutions, our approach could obtain similar results with significant speed-up.