A Low Power Highly Associative Cache for Embedded Systems

Author

Zhang, Chuanjun

Author_Institution

Missouri Univ., Kansas

fYear

2007

fDate

1-4 Oct. 2007

Firstpage

31

Lastpage

36

Abstract

Reducing energy consumption is an important issue for battery powered embedded computing systems. Content addressable memory (CAM)-based highly-associative caches (HAC) are widely used in low power embedded microprocessors. The CAM tag is costly in power, access time, and area. We have designed a low power highly associative cache (LPHAC) whose tag is partially implemented by using CAM, while the remaining tag is implemented by using SRAM. The experimental results from 10 MediaBench and all 26 SPEC2K benchmarks show the proposed LPHAC exhibits almost the identical miss rate as a traditional HAC. At the same time, it consumes 27% less per cache access power and 1.6% less area with faster access time.

Keywords

cache storage; content-addressable storage; embedded systems; logic design; low-power electronics; microprocessor chips; CAM; battery powered embedded computing system; content addressable memory; energy consumption; logic design; low power highly associative cache; microprocessor; CADCAM; Cache memory; Circuits; Computer aided manufacturing; Computer architecture; Embedded computing; Embedded system; Energy consumption; Microprocessors; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2006. ICCD 2006. International Conference on

Conference_Location

San Jose, CA

ISSN

1063-6404

Print_ISBN

978-0-7803-9707-1

Electronic_ISBN

1063-6404

Type

conf

DOI

10.1109/ICCD.2006.4380790

Filename

4380790