Title :
Design and implementation of transaction level processor based on UVM
Author :
Yingke Gao ; Diancheng Wu ; Quanquan Li ; Tiejun Zhang ; Chaohuan Hou
Author_Institution :
Digital Syst. Integration Lab., Inst. of Acoust., Beijing, China
Abstract :
As the complexity of integrated circuit increases, the transaction level model (TLM) bridges the architecture and the hardware implementation. With SuperV_EF01 DSP as the research prototype, this paper presents a new method to design and implement the transaction level model based on UVM, which provides plenty of SystemVerilog libraries. This model can accelerate software development and be used as a golden reference model in the verification of RTL model without complex interface function.
Keywords :
digital signal processing chips; integrated circuit modelling; program verification; transaction processing; RTL model verification; SuperV_EF01 DSP; SystemVerilog libraries; TLM; UVM; golden reference model; integrated circuit complexity; software development; transaction level model; transaction level processor; Computational modeling; Computer architecture; Hardware; Integrated circuit modeling; Software; Time-domain analysis; Time-varying systems; SuperV_EF01; TLM; UVM; reference model; software development; verification;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6811924
