25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter

To support 16-QAM modulation in E-band applications, phase-locked loops (PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed to scale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by the op-amp. Moreover, as the capacitance is reduced, the resistor value has to be increased to maintain the same zero frequency, leading to higher thermal noise and limiting achievable scaling factor. Another method is to integrate digital loop filters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise of digitally-controlled oscillators (DCOs) becomes a bottleneck to achieve good phase noise due to their limited frequency resolution. Furthermore, E-band DCO oscillation frequency is more sensitive to capacitor variation, making it even more difficult to achieve high frequency resolution. To address these issues, this paper proposes a 70.5-to-85.5GHz PLL with an injection-locked frequency tripler (ILFM3) and passive scaling to increase the effective capacitor for the loop filter by 100 times.