The timing control design of 65nm block RAM in FPGA

The timing control design of 65 nm-based FPGA embedded Block RAM is presented. The strategy involves both the internal timing control system with test reliability considered and the status flag timing control of BRAM-based FIFO. With redundant circuits using dynamic feedback ideology, introducing an optional delay chain optimization and optimizing clock latency strategies, the strategy guarantees the reliability of timing control in BRAM. Meanwhile, optimizing speed makes the proposed design practical. The proposed BRAM can work in a variety of work environments correctly and maximize success rate of tapeout. It is 41.5%~59.2% deceasing in control delay than that in the structure of Ref [7]. BRAM with novel timing control design is designed with the speed of 400 MHz, which is 25% faster than that in Ref [9].