A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC

Author

Ting Li ; Dongbing Fu ; Yong Zhang ; Yan Wang ; Lu Liu ; Xu Wang

Author_Institution

Sci. & Technol. on Analog Integrated Circuit Lab., Chongqing, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 1.8V/3.3V supply of a 0.18um BiCMOS process.

Keywords

BiCMOS integrated circuits; analogue-digital conversion; feedback amplifiers; high-speed integrated circuits; pipeline arithmetic; BiCMOS process; amplifier; double duty cycle; duty cycle stabilizer; feedback factor; frequency 25.39 MHz; high-speed front-end circuit design; pipeline ADC; pipeline analog-to-digital circuit; sampling networks; size 0.18 mum; voltage 1.8 V to 3.3 V; word length 16 bit; Capacitors; Circuit synthesis; Clocks; Equations; Pipelines; Power demand; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811964

Filename

6811964