SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages

Technology scaling brings lower supply voltages. For advanced CMOS technology nodes of 40nm and beyond, this leads to specific challenges. In particular, analog circuits require specialized design approaches and innovative techniques. Maintaining high precision with reduced available signal swing while keeping energy consumption within reasonable bounds has presented challenges for many circuit designers. Increased technological variability and leakage only make this worse.