A transition language for scheduling analysis in operator design methodology

Nowadays, with the processing technology of integrated circuits(IC) developing into deep sub-micron size and the scale of IC running into VLSI, the existing IC design methodology can hardly meet the demands for short time-to-market and continuous increasing functionality of IC products. Facing with these challenges, researchers all around the world have been chasing rapid design methods such as reconfigurable processor and high-level synthesis (HLS). In this paper, a transitional language for scheduling analysis in operator design methodology, which is a novel scheme of HLS, is proposed. With the help of the proposed transition language, an algorithm developed with high-level language can be transformed into hardware description automatically or half-automatically. The experiment results by applying a widely used target algorithm in the academic HLS field prove the feasibility and efficiency of the operator design methodology and also the proposed transition language comparing with that of the SPARK HLS tool developed by UC San Diego.