DocumentCode
2067181
Title
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing
Author
Ningxi Liu ; Yu Jiang ; Qing Dong ; Hui Li ; Xinyi Hu ; Yinyin Lin
Author_Institution
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
fYear
2013
fDate
28-31 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
Adaptive VSS boosting with process variation compensation is proposed to reduce the standby leakage by 6X at room temperature and improves the write static noise margin. The N-pulse read assist circuit enables higher read stability and faster read speed. The systematic BL capacitance variation is detected, and a proper WL voltage is generated to mitigate the BL discharging speed variation by 20%.
Keywords
SRAM chips; logic design; low-power electronics; BL capacitance variation sensing; VSS adaptive boosting; low-power high-yield SRAM design; static noise; Arrays; Boosting; Capacitance; Partial discharges; SRAM cells; Wireless sensor networks; High yield; Low power; Speed variation;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location
Shenzhen
ISSN
2162-7541
Print_ISBN
978-1-4673-6415-7
Type
conf
DOI
10.1109/ASICON.2013.6811968
Filename
6811968
Link To Document