A Pattern Generation Technique for Maximizing Power Supply Currents

Max-current analysis is essential in power rail design and power supply switching noise analysis. Traditionally, maximum current from all CMOS gates are added together to compute maximum current level. This approach ignores all Boolean relationships. The problem of finding the input vector pair that will cause worst case current draw from the power rails when Boolean relationships are considered is an NP-hard problem. In this paper, we propose a Current Maximizing Pattern Generation (CMPG) algorithm which greatly reduces the computational complexity by using a parameterized branch-and-bound heuristic that prunes the search space by looking for a lower as well as an upper bound for maximum switching currents. When allowed to proceed indefinitely, the CMPG algorithm converges on an exact solution instead of finding upper and lower bounds. When coupled with a switch level SAT solver, CMPG can generate patterns for cell library characterization.