Title :
A 50 MHz vision processor
Author :
Sutardja, Sehat ; Fandrianto, Jan ; Martin, Bryan ; Rainnie, Hedley ; Wang, Chi-Shin
Author_Institution :
Integrated Inf. Technol., Santa Clara, CA, USA
Abstract :
A highly integrated microcoded motion video (de)compression digital signal processing chip that can perform 800×106 16-b multiply, shift, and accumulate operations, 800×106 pixel absolute difference operations or 400×106 16-b addition-subtraction operations, and 800×106 sum of difference operations in each second is described. The chip has been fabricated in a 1-μm CMOS technology and has been tested to run at 50 MHz. When coupled with external interface circuitry, the vision processor is suitable for use in many consumer and desktop multimedia applications
Keywords :
CMOS integrated circuits; computerised picture processing; digital signal processing chips; multimedia systems; 1 micron; CMOS technology; absolute difference operations; accumulate operations; addition-subtraction operations; desktop multimedia applications; digital signal processing chip; microcoded motion video decompression; sum of difference operations; vision processor; Digital signal processing chips; Discrete cosine transforms; Engines; Information technology; Motion estimation; Random access memory; Reduced instruction set computing; Registers; Teleconferencing; Video compression;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164023
