A wave-pipelined on-chip interconnect structure for networks-on-chips

The paper describes a structured communication link design technique, wave-pipelined interconnect, for networks-on-chip. We achieved 3.45 GHz and 55.2 Gbps throughput on a 10 mm 16 bit interconnection in a 0.25 μm technology. It uses 0.079 mm² of area, and it only needs 18.8 pJ to transmit one bit. We reduce crosstalk delay 79% by using two techniques - interleaved lines and misaligned repeaters. This paper shows, in detail, the various techniques we used to save power and area and achieve high performance in a relatively old technology. Wave-pipelined interconnect design is relatively easy, but its many features give a large and flexible design space for high-performance chips.