Low power design for FIR filter

Author

Gaowei Xu ; Yao Zou ; Jun Han ; Xiaoyang Zeng

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.

Keywords

FIR filters; low-pass filters; low-power electronics; multiplying circuits; pipeline arithmetic; fixed point finite impulse response digital filters; low-pass FIR filter; low-power design; multihierarchy pipeline design; optimal CSD encoding; size 65 nm; word length 16 bit; Algorithm design and analysis; Encoding; Filtering algorithms; Finite impulse response filters; Power demand; Signal processing algorithms; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811978

Filename

6811978