Title :
Three-tier PoP configuration utilizing flip chip Fan-in PoP bottom package
Author :
Carson, Flynn ; Ishibashi, Kazuo ; Kim, Yeong Cheol
Author_Institution :
STATS ChipPAC Inc., Fremont, CA
Abstract :
The increasing demand for functionality and performance in mobile handsets has driven the requirement for separate modem and application processors with requisite memory. PoP has helped reduce the footprint of each processor and memory package combination on the PCB. Stacking the processors and memory in a single three-tier PoP configuration would further reduce the footprint. This paper details the development of such a three-tier PoP configuration, utilizing Fan-in PoP technology for the bottom PoP. The developed three-tier PoP test vehicle successfully exhibited good surface mount yield and excellent board level drop test and temperature cycle performance.
Keywords :
electronics packaging; flip-chip devices; mobile handsets; printed circuits; surface mount technology; PCB; board level drop test; flip chip fan-in PoP bottom package; memory package combination; mobile handsets; package-on-package; processors; surface mount yield; three-tier PoP configuration; Electronics packaging; Flip chip; Handheld computers; Logic devices; Mobile handsets; Modems; Stacking; Temperature; Testing; Vehicles;
Conference_Titel :
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-4475-5
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2009.5074033
