DocumentCode
2067574
Title
A FPGA real-time stereo vision system with luminance control and projected pattern
Author
Xu Yuan ; Yao Haodong ; Gong Liwei ; Zhu Mingcheng ; Teng, Robert K. F.
Author_Institution
Shenzhen Key Lab. of Adv. Commun. & Inf. Process., Shenzhen Univ., Shenzhen, China
fYear
2013
fDate
28-31 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
This paper presents a real-time stereo video processing system based on FPGA. The system takes rectification and histogram equalization as its pre-processing, and the depth detection of this system is using generalized census transform and block matching method. With the help of on-line generated projected pattern by the pattern controller inside FPGA, this system can be used in various environments. The median filter is used as the post-processing step of depth map. In comparison to the software solution method, this system takes the advantage of the parallel nature of FPGA and got higher speed in generating the depth map. Therefore, it can be applied to the applications demanded for better performance.
Keywords
equalisers; field programmable gate arrays; image sensors; median filters; rectification; stereo image processing; transforms; visual perception; FPGA real-time stereo vision system; block matching method; depth detection; depth map post-processing step; generalized census transform method; histogram equalization; luminance control; median filter; online generated projected pattern; pattern controller; real-time stereo video processing system; rectification; software solution method; Field programmable gate arrays; Hamming distance; Hardware; Histograms; Real-time systems; Stereo vision; Transforms; FPGA; generalized census; projected texture; stereo vision;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location
Shenzhen
ISSN
2162-7541
Print_ISBN
978-1-4673-6415-7
Type
conf
DOI
10.1109/ASICON.2013.6811983
Filename
6811983
Link To Document