DocumentCode
2067648
Title
A sub-micron CMOS embedded SRAM compiler
Author
Tou, Jarvis ; Gee, Perry ; Duh, John ; Eesley, Rick
Author_Institution
Motorola Inc., Chandler, AZ, USA
fYear
1991
fDate
12-15 May 1991
Abstract
The authors describe the Memorist SRAM compiler, a highly flexible memory generation system that produces high-speed, high-density synchronous single or dual port static diffused memories embedded in a gate array environment. It provides for accurate timing characterization and is lightly integrated into an ASIC (application-specific integrated circuit) development system. Embedded memories up to 256K bits can be achieved
Keywords
CMOS integrated circuits; SRAM chips; application specific integrated circuits; circuit layout CAD; 256 kbit; ASIC development system; Memorist; application-specific integrated circuit; dual port; embedded SRAM compiler; gate array environment; high density synchronous memory; single-port type; static diffused memories; submicron CMOS; timing characterization; Application specific integrated circuits; Central Processing Unit; Character generation; Clocks; Design engineering; Random access memory; Read-write memory; Synchronous generators; Timing; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164024
Filename
164024
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