A novel architecture of local memory for programmable SIMD vision chip

This paper presents a novel architecture of the local memory for the programmable SIMD vision chip. The memory architecture consists of 8 × 8 local memory cells, among which each 8 static latches in the master stage share one dynamic latch in the slave stage. The local memory performs single bit read and write in each clock cycle, and the compact area of 14.33 μm²/bit increases the integration level of the processor. A prototype chip with 64 × 64 processing units has been manufactured in 0.18 μm CMOS technology. Five types of local memory architecture have been designed, and an 8-bit input data buffer based on dedicated latch structures has been designed as the input data buffer for each processing unit. Test results show that the presented structure is suitable for real-time computer vision applications such as the edge detection at the speed of 1000 fps.