Memory hardware support for sparse computations

Address computations and indirect, hence double, memory accesses in sparse matrix application software render sparse computations to be inefficient in general. The authors propose memory architectures that support the storage of sparse vectors and matrices. In a first design, called vector storage, a matrix is handled as an array of sparse vectors, stored as singly-linked lists. Deletion and insertion of a vector is done row-or column-wise only. In a second design, called matrix storage, a higher level of sophistication is achieved. A sparse matrix is stored as a bi-directionally threaded doubly-linked list of elements. This approach enables both row- and column-wise operations. A pipelined variant with 3-fold interleaved memory and write buffers yields high efficiency, close to one sparse matrix element per memory cycle for all basic vector operations.<>