DocumentCode
2067805
Title
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform
Author
Qing Zhang ; Yu Xueqiu ; Yu Zhiyi ; Xiaoyang Zeng
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2013
fDate
28-31 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
This paper presents an implementation of turbo decoder in LTE downlink system on a multi-core processor platform. Turbo code, also called Parallel Concatenated Convolutional Code (PCCC) is used for LTE system [1] for its good error correcting ability and anti-interference ability [2]. As the wireless communication is developing constantly, it turns to be more difficult for ASIC baseband processing solutions to adapt the rapidly changing communication standards. The multi-core processor platform, a mesh array of SIMD cores, is well suited for wireless communication applications due to its programmability and re-configurability. We realize a turbo decoder with the throughput of 46Mbps by deeply excavating the task-level pipelining and data-level parallelism on multi-core processor platform.
Keywords
Long Term Evolution; convolutional codes; multiprocessing systems; parallel processing; radio links; telecommunication computing; turbo codes; ASIC baseband processing; LTE downlink system; PCCC; SIMD cores; antiinterference ability; data level parallelism; error correcting ability; mesh array; multicore processor platform; parallel concatenated convolutional code; task level pipelining; turbo code; turbo decoder implementation; wireless communication; wireless communication applications; Decoding; Downlink; Long Term Evolution; Measurement; Multicore processing; Throughput; Turbo codes;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location
Shenzhen
ISSN
2162-7541
Print_ISBN
978-1-4673-6415-7
Type
conf
DOI
10.1109/ASICON.2013.6811992
Filename
6811992
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