DocumentCode
2067866
Title
Improvements to the ETS dynamic dataflow architecture
Author
Patadia, Phenil ; Karani, Vijay ; Kavi, Krishna ; Shanmugam, Ponnarasu ; Shirazi, Behrooz ; Hurson, Ali R.
Author_Institution
Texas Univ., Arlington, TX, USA
Volume
1
fYear
1994
fDate
4-7 Jan. 1994
Firstpage
378
Lastpage
387
Abstract
This paper discusses an enhancement to on Explicit Token Store (ETS) dataflow architecture by a variation in token format. As a hypothetical machine model, the experiment shows that the proposed variation achieved better performance by reducing the number of instruction references while maintaining same fine grained parallism of ETS architecture. The ability of the token formation unit to form two tokens for every matched token is exploited by using multiple fetch units. The results of the simulation demonstrate the ability of multiple fetch units in increasing the throughput and reducing pipeline bubbles through the ALU. Our results indicate that it is possible to implement dataflow model of execution and achieve RISC-like "one instruction per cycle" performance.<>
Keywords
parallel processing; performance evaluation; reduced instruction set computing; ALU; Explicit Token Store dataflow architecture; RISC; dataflow model; fine grained parallism; hypothetical machine model; instruction references; multiple fetch units; performance; pipeline bubbles; token format;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1994. Proceedings of the Twenty-Seventh Hawaii International Conference on
Conference_Location
Wailea, HI, USA
Print_ISBN
0-8186-5090-7
Type
conf
DOI
10.1109/HICSS.1994.323146
Filename
323146
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