V++: an instruction-restructurable processor architecture

It is essential to extract fine grain parallelism for further increase of processor performance. This paper investigates an extension model of VLIW architecture called V++, which retains the capabilities of VLIW architecture to effectively exploit fine grain parallelism while introducing facilities for restructuring very long instruction words dynamically. V++ adopts two types of restructuring methods: one is predetermined restructuring, which is realized by delaying certain operations on the basis of the information generated by the compiler, and the other is adaptive restructuring, which is controlled by the high-speed synchronization mechanism called Ultimate barrier.<>