The decimator with multiplier-free realizations for high precision ADC applications

Aiming at the medical application of high precision ECG signal acquisition, an efficient decimator in 18-bit Σ-Δ ADC with multiplier-free methods is presented. The decimator can be applied with the single loop, multi-loop or cascade Σ-Δ modulator (SDM). For efficient hardware implementation of the proposed decimator, the Rom-ram construction with CSD decoder is designed instead of the MAC filtering, while the TDM-based cascade of C-DF and single-rate half-band filter is established. To further improve the execution efficiency, a novel multiplier-free approach is employed in multi-rate half-band filter, by synthesizing the filter into sub-filters with only a few powers-of-two representation forms for tap coefficients. As results, the decimator achieves real time processing of 325Hz-baseband ECG signal, with low latency, high filtering performance and low resource cost.