A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design

The processors´ architecture design plays an important role in high performance DSP era, where how to balance the power consumption and the computing ability is always a great concern. In this paper we propose an architecture scheme with VLIW instruction driven adaptive pipeline coupling technique for a multi-core processor design to achieve the high computing performance with a low powered capability. Combined with the loop buffering design and implementation, the scheme is evaluated with the typical DSP application and the results show that the performance is improved about 43.4% while the power consumption is reduced by 48.7% in average.