Title :
A 7 MHz 24-bit pipelined accumulator in 1.2-μm CMOS for application as a numerically controlled oscillator
Author :
Lu, Fang ; Samueli, Henry ; Yuan, Jiren ; Svensson, Christer
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) chip using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The 1.7-mm×1.7-mm IC has a maximum input clock rate of 700 MHz and dissipates 850 mW of power, which is substantially lower than similar ECL and GaAs devices. The digital NCO technique results in a frequency-tuning resolution and open-loop control linearity which cannot be achieved by analog approaches
Keywords :
CMOS integrated circuits; digital integrated circuits; oscillators; pipeline processing; tuning; 1.2 micron; 700 MHz; 850 mW; CMOS process; circuit design technique; frequency-tuning resolution; high-speed communication systems; numerically controlled oscillator; open-loop control linearity; pipelined accumulator; single-phase clock; timing recovery; timing synthesis; CMOS process; Circuit synthesis; Clocks; Communication standards; Communication system control; Control system synthesis; Frequency; Gallium arsenide; Oscillators; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164026
